A collection of code generation tools which assist designers in the functional verification of high performance microprocessors is presented. These tools produce interesting test cases by using a variety of code generation methods including heuristic algorithms, constraint-solving systems, user-provided templates, and pseudo-random selection. Run-time… (More)
This paper describes the implementation and the performance study of three parallel discrete event simulation methods on a shared memory machine. These methods, which share a single user interface, include the Chandy-Misra paradigm with deadlock avoidance; the Time Warp approach with direct, aggressive, and lazy cancellation; and a hybrid approach, which… (More)
This paper presents a verification methodology for configurable processor cores. The simulation-based approach uses directed diagnostics and pseudo-random program generators both of which are tailored to specific processor instances. A configurable and extensible test-bench serves as the framework for the verification process and offers components necessary… (More)
A new partitioning method for synchronous PDES simulations is proposed. The method exploits characteristics of both the simulation method and of the application domain to arrive at efficient partitionings. A performance study shows that the method outperforms existing partitioning methods in terms of four different performance metrics.
Chief is a comprehensive, integrated simulation environment for studying all aspects of parallel system design and performance evaluation including architectures, compilers, algorithms and applications, and simulation techniques. Chief provides this level of functionality through the integration of restructuring / parallelizing compilers, trace generation… (More)
A simulation environment which combines object-oriented software engineering, parallel processing, and parallel simulation is presented. The layered nature of the environment allows us to address the issues of software rnanageabilityandex-ecution speed independently, and, at the same time, integrate them into a complete solution to parallel simulation. The… (More)
This paper describes a novel data structure and an algorithm for processor self-scheduling in parallel discrete event simulation. The presented data structure allows the efficient scheduling of future computations, it facilitates the inexpensive use of processor affinity information, it reduces the contention on the scheduling queue, and it integrates load… (More)