Pavel G. Zaykov

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Engineers who design hard real-time embedded systems express a need for several times the performance available today while keeping safety as major criterion. A breakthrough in performance is expected by parallelizing hard real-time applications and running them on an embedded multi-core processor, which enables combining the requirements for(More)
<i>Integrated Modular Avionics</i> (IMA) enables incremental qualification by encapsulating avionics applications into <i>software partitions</i> (SWPs), as defined by the ARINC 653 standard. SWPs, when running on top of single-core processors, provide <i>robust time partitioning</i> as a means to isolate SWPs timing behavior from each other. However, when(More)
This paper provides a survey on the existing proposals in the field of reconfigurable multithreading (ρMT) architectures. Until now, the reconfigurable architectures have been classified according to implementation or architectural criteria, but never based on their ρMT capabilities. More specifically, we identify reconfigurable architectures that provide(More)
Parallel multi-threaded applications are needed to gain advantage from multi- and many-core processors. Such processors are more frequently considered for embedded hard real-time with defined timing guarantees, too. The static timing analysis, which is one way to calculate the worst-case execution time (WCET) of parallel applications, is complex and(More)
The EC project parMERASA (Multicore Execution of Parallelized Hard Real-Time Applications Supporting Analyzability) investigated timing-analyzable parallel hard real-time applications running on a predictable multicore processor. A pattern-supported parallelization approach was developed to ease sequential to parallel program transformation based on(More)
This report provides a survey on the existing proposals in the field of reconfigurable multithreading architectures (ρMT). Until now, the reconfigurable architectures have been classified according to implementation or architectural criteria, but never based on their ρMT capabilities. More specifically, we identify reconfigurable architectures that provide(More)
In hard real-time systems, such as avionics, there is demand for high performance. A way to meet performance demands is by parallel computation on multicore systems. A main contributor for the application performance on multicore systems is size and type of cache memory. For multicore hard real-time systems, the usage of cache memory is problematic.(More)
Low energy consumption is crucial for embedded systems, including the ones that employ tiled Multiprocessor Systems-on-Chip(MPSoC). Such systems often execute real-time applications consisting of several tasks synchronized in a data-flow manner and mapped over different MPSoC tiles. Energy can be saved by lowering the processor voltage and frequency, hence(More)