Paulo C. de Aguirre

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This paper presents the characterization and synthesis results for a hardware implementation of a reconfigurable digital logic cancellation circuit auxiliary for multi-mode Σ∆ modulator that is capable to perform the analog-to-digital conversion for GSM, CDMA and WLAN standards. The Σ∆ modulator reconfigures its mash topology and building blocks in order to(More)
This paper presents a reconfigurable digital design of filtering and decimation for a cascade 2-2 sigmadelta ( ) analog-to-digital converter (ADC). The ADC reconfigures its MASH (Multi-Stage-NoiseShaping) topology and building blocks in order to adapt the bandwidth requirements to diverse standard specifications. This reconfigurable design is composed by a(More)
This paper presents a digitally tunable 4th-order Gm-C low-pass filter (LPF) for multi-standards radio receivers. The cutoff frequency tuning is provided by changing the transconductance of a reconfigurable operational transconductance amplifier (OTA). Two control bits are employed to digitally control the OTA transconductance and also the power(More)
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