Paula Ning

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—This paper compares 130nm custom silicon implementations of three scalable Montgomery multiplier architectures to previously published FPGA implementations of the same architectures. It investigates the delay, energy, and area trade-offs of parallelized left-shifting radix-2, radix-4, and Booth-encoded radix-4 architectures. The radix-4 architecture is(More)
—In 2004, Robert Jackson and Sunil Talwar published a novel method of decomposing binary prefix addition. Their work sought to balance the complexity of the generate and propagate terms that bear the computational load in parallel prefix adders. This paper presents an implementation of a 64-bit adder based on this method, as well as an improved method of(More)
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