Paul Theo Gonciari

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This paper presents a new compression method for embedded core-based system-on-a-chip test. In addition to the new compression method, this paper analyzes the three test data compression environment (TDCE) parameters: compression ratio, area overhead and test application time, and explains the impact of the factors which influence these three parameters.(More)
This paper proposes a new test data compression/decompression method for systems-on-a-chip. Themethod is based on analyzing the factors that influencetest parameters: compression ratio, area overhead and testapplication time. To improve compression ratio, the newmethod is based on a Variable-length Input Huffman Coding(VIHC), which fully exploits the type(More)
Driven by the industrial need for low-cost test methodologies, the academic community and the industry alike have put forth a number of efficient test data compression (TDC) methods. In addition, the need for core-based System-on-a-Chip (SoC) test led to considerable research in test access mechanism (TAM) design. While most previous work has considered TAM(More)
Test data compression is an enabling technology for low-cost test. Compression schemes however, require communication between the system under test and the automated test equipment. This communication, referred to in this paper as synchronization overhead, may hinder the effective deployment of this new test technology for core-based systems-on-a-chip. This(More)
This paper investigates the relationship between test data compression and power dissipation during scan testing. It is shown how combining a recently proposed symmetric coding scheme and a new weighted scan latch reordering (W-SLR) algorithm, leads to efficient exploration in the scan power and test data compression solution space. This is achieved by(More)
This paper discusses an integrated solution for reducing the volume of test data for deterministic system-on-achip testing. The proposed solution is based on a new test data decompression architecture which exploits the features of a core wrapper design algorithm targeting the elimination of useless test data. The compressed test data can be transferred(More)
Synchronization overhead between the core under test and the automatic test equipment is the main drawback of test data compression/decompression environments, which hinders the deployment of this new embedded test technology. This paper introduces two new methods to reduce the synchronization overhead. Firstly, the synchronization overhead is reduced by(More)
This paper analyzes the test memory requirements for core-based systems-on-a-chips and identifies useless test data as one of the contributors to the total amount of test data. The useless test data comprises the padding bits necessary to compensate for the difference between the lengths of different chains in multiple scan chains designs. Although useless(More)
Test data compression (TDC) is a promising low-cost methodology for System-on-a-Chip (SOC) test. This is due to the fact that it can reduce not only the volume of test data but also the bandwidth requirements. In this paper we provide a quantitative analysis of two distinctive TDC methods from the system integratorýs standpoint considering a core based(More)