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In 3-D interconnect structures, process-induced thermal stresses around through-silicon-vias (TSVs) raise serious reliability issues such as Si cracking and performance degradation of devices. In this study, the thermo-mechanical reliability of 3-D interconnect was investigated using finite element analysis (FEA) combined with analytical methods. FEA(More)
Holliday junctions are important structural intermediates in recom-bination, viral integration, and DNA repair. We present here the single-crystal structure of the inverted repeat sequence d(CCGG-TACCGG) as a Holliday junction at the nominal resolution of 2.1 Å. Unlike the previous crystal structures, this DNA junction has B-DNA arms with all standard(More)
—Continual scaling of on-chip wiring structures has brought significant challenges for materials and processes beyond the 32-nm technology node in microelectronics. Recently, 3-D integration with through-silicon vias (TSVs) has emerged as an effective solution to meet the future interconnect requirement. Among others, thermomechanical reliability is a key(More)
In this paper we investigated the interfacial delamination of through silicon via (TSV) structures under thermal cycling or processing. First finite element analysis (FEA) was used to evaluate the thermal stresses and the driving force of TSV delamaination. Then, the modeling results were validated by analytical solutions of the crack driving force deduced(More)
Mechanism for resistive switching in an oxide-based electrochemical metallization memory Appl. The role of eddy currents and nanoparticle size on AC magnetic field–induced reflow in solder/magnetic nanocomposites J. Characterization of thermal stresses in through-silicon vias for three-dimensional interconnects by bending beam technique Appl.(More)
—This paper investigates two key aspects of thermomechanical reliability of through-silicon vias (TSV) in 3D interconnects. One is the piezoresistivity effect induced by the near surface stresses on the charge mobility for p-and n-channel MOSFET devices. The other problem concerns the interfacial delamination induced by thermal stresses including the pop-up(More)
Chip-packaging interaction is becoming a critical reliability issue for Cu/low k chips during package assembly. With the traditional TEOS interlevel dielectric being replaced by much weaker low k dielectrics, packaging induced interfacial delamination in low k interconnects has been widely observed, raising serious reliability concerns for Cu/low k chips.(More)
— The paper describes a 4-MHz temperature compensated reference oscillator based on a capacitive silicon micro-mechanical resonator. The design of the resonator has been optimized to offer large quality factors (22000), while maintaining tunability in excess of 3000ppm for fine tuning and temperature compensation. Oscillations are sustained with a CMOS(More)
In this paper, temperature-dependent thermal stresses in Cu TSVs are measured by combining the bending beam experiment with a finite element analysis (FEA). The bending beam technique measures the averaged bending curvature induced by the thermal expansion of a periodic annular Cu TSV array. The structural complexity of the blind annular TSV necessitated(More)