Paul S. Ho

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— The paper describes a 4-MHz temperature compensated reference oscillator based on a capacitive silicon micro-mechanical resonator. The design of the resonator has been optimized to offer large quality factors (22000), while maintaining tunability in excess of 3000ppm for fine tuning and temperature compensation. Oscillations are sustained with a CMOS(More)
In most cases authors are permitted to post their version of the article (e.g. in Word or Tex form) to their personal website or institutional repository. Authors requiring further information regarding Elsevier's archiving and manuscript policies are encouraged to visit: a b s t r a c t A comprehensive kinetic analysis was established to investigate the(More)
Chip-packaging interaction is becoming a critical reliability issue for Cu/low k chips during package assembly. With the traditional TEOS interlevel dielectric being replaced by much weaker low k dielectrics, packaging induced interfacial delamination in low k interconnects has been widely observed, raising serious reliability concerns for Cu/low k chips.(More)
This letter demonstrates a method for fabricating single-crystal Si nanolines, with rectangular cross sections and nearly atomically flat sidewalls. The high quality of these nanolines leads to superb mechanical properties, with the strain to fracture measured by nanoindentation tests exceeding 8.5% for lines of 74 nm width. A large displacement burst(More)
Three-dimensional (3-D) integration with through-silicon-vias (TSVs) has emerged as an effective approach to overcome the wiring limit beyond the 32 nm technology node. Due to the mismatch of thermal expansion between the via material and Si, thermal stresses ubiquitously exist in the integrated 3-D structures. The thermal stresses can be significant to(More)
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