Paul S. Graham

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With the introduction of Splash, Splash 2, PAM, and other reconngurable computers, a wide variety of algorithms can now be feasibly constructed in hardware. In this paper, we describe the Splash 2 Parallel Genetic Algorithm (SPGA), which is a parallel genetic algorithm for optimizing symmetric traveling salesman problems (TSPs) using Splash 2. Each(More)
This paper presents the application of time-delay sonar beamforming and discusses a multi-board FPGA system for performing several variations of this beamforming method in real-time for realistic sonar arrays. Additionally, we show that our proposed FPGA system has a six to twelve times performance advantage over an equivalent system created using currently(More)
This paper analyzes the performance diierences found between the hardware and software versions of a genetic algorithm used to solve the traveling salesman problem. The hardware implementation requires 4 FPGA's on a Splash 2 board and runs at 11 MHz. The software implementation was written in C++ and executed on a 125 MHz HP PA-RISC workstation. The(More)
— This paper describes novel methods of exploiting the partial, dynamic reconfiguration capabilities of Xilinx Virtex V1000 FPGAs to manage single-event upset (SEU) faults due to radiation in space environments. The on-orbit fault detection scheme uses radiation-hardened reconfiguration controllers to continuously monitor the configuration bitstreams of 9(More)
Since FPGAs are frequently used to improve the time to market for products, shortening the time for validating and debugging FPGA designs is, thus, important. Our paper discusses how directly instrumenting FPGA programming data, or bitstreams, with debugging hardware can improve the debugging productivity for designers and, thus, reduce a design's time to(More)
This paper describes a structured technique for providing full observability and controllability for functionally debugging FPGA designs in hardware, capabilities which are currently not available otherwise. Similar in concept to flip-flop scan chains for VLSI, our design-level scan technique includes all FPGA flip-flops and RAMs in a serial scan chain(More)