Paul S. Graham

Learn More
This paper describes an efficient approach of applying mitigation to an FPGA design to protect against Single Event Upsets (SEUs). This approach applies mitigation selectively to FPGA circuit structures depending on the importance of structure within the design. Higher priority is given to structures causing “persistent” errors within the design. For(More)
Understanding the SEU induced failure modes specific to the Virtex SRAM FPGA is needed to evaluate the applicability of various mitigation schemes since many mitigation approaches were originally intended for ASICs and may not be effective or efficient within FPGAs due to the unique failure modes and architectures found in SRAM-based FPGAs. Through this(More)
Since FPGAs are frequently used to improve the time to market for products, shortening the time for validating and debugging FPGA designs is, thus, important. Our paper discusses how directly instrumenting FPGA programming data, or bitstreams, with debugging hardware can improve the debugging productivity for designers and, thus, reduce a design’s time(More)
With the introduction of Splash, Splash 2, PAM, and other reconngurable computers, a wide variety of algorithms can now be feasibly constructed in hardware. In this paper, we describe the Splash 2 Parallel Genetic Algorithm (SPGA), which is a parallel genetic algorithm for optimizing symmetric traveling salesman problems (TSPs) using Splash 2. Each(More)
This paper provides a methodology for estimating the proton and heavy ion static saturation crosssections for multi-bit upsets (MBUs) in Xilinx fieldprogrammable gate arrays (FPGAs) and describes a methodology for determining MBUs’ effects on triplemodular redundancy (TMR) protected circuits. Experimental results are provided.
Summary form only given. We describe novel methods of exploiting the partial, dynamic reconfiguration capabilities of Xilinx Virtex 1000 FPGAs to manage transient faults due to radiation in space environments. The on-orbit fault detection scheme uses a radiation-hardened reconfiguration controller to continuously monitor the configuration bit streams of 9(More)
This paper presents the application of time-delay sonar beamforming and discusses a multi-board FPGA system for performing several variations of this beamforming method in real-time for realistic sonar arrays. Additionally, we show that our proposed FPGA system has a six to twelve times performance advantage over an equivalent system created using currently(More)
This paper analyzes the performance diierences found between the hardware and software versions of a genetic algorithm used to solve the traveling salesman problem. The hardware implementation requires 4 FPGA's on a Splash 2 board and runs at 11 MHz. The software implementation was written in C++ and executed on a 125 MHz HP PA-RISC workstation. The(More)