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— This paper provides a methodology for estimating the proton and heavy ion static saturation cross-sections for multi-bit upsets (MBUs) in Xilinx field-programmable gate arrays (FPGAs) and describes a methodology for determining MBUs' effects on triple-modular redundancy (TMR) protected circuits. Experimental results are provided.
strongly supports academic freedom and a researcher's right to publish; as an institution, however, the Laboratory does not endorse the viewpoint of a publication or guarantee its technical correctness. Abstract— Understanding the SEU induced failure modes specific to the Virtex SRAM FPGA is needed to evaluate the applicability of various mitigation schemes(More)
Problems with terrestrial-based neutron radiation from cosmic rays have become more commonplace. While the incident rate from neutron radiation is lower than space-based radiation, physics, system design and system locations have combined to make systems increasingly vulnerable to terrestrial radiation. FPGA systems are particularly sensitive to neutron(More)
strongly supports academic freedom and a researcher's right to publish; as an institution, however, the Laboratory does not endorse the viewpoint of a publication or guarantee its technical correctness. Abstract: This paper provides a methodology for estimating the proton static cross-section for multi-bit upsets (MBUs) in Xilinx FPGAs and describes a(More)
— This paper describes an efficient approach of applying mitigation to an FPGA design to protect against Single Event Upsets (SEUs). This approach applies mitigation selectively to FPGA circuit structures depending on the importance of structure within the design. Higher priority is given to structures causing " persistent " errors within the design. For(More)
With the introduction of Splash, Splash 2, PAM, and other reconngurable computers, a wide variety of algorithms can now be feasibly constructed in hardware. In this paper, we describe the Splash 2 Parallel Genetic Algorithm (SPGA), which is a parallel genetic algorithm for optimizing symmetric traveling salesman problems (TSPs) using Splash 2. Each(More)
This paper presents the application of time-delay sonar beamforming and discusses a multi-board FPGA system for performing several variations of this beamforming method in real-time for realistic sonar arrays. Additionally, we show that our proposed FPGA system has a six to twelve times performance advantage over an equivalent system created using currently(More)
strongly supports academic freedom and a researcher's right to publish; as an institution, however, the Laboratory does not endorse the viewpoint of a publication or guarantee its technical correctness. Abstract Field programmable gate arrays (FPGAs) are an attractive alternative for space-based remote sensing applications. However, SRAM-based FPGAs are(More)