Paul S. Andry

Learn More
of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection J. U. Knickerbocker P. S. Andry L. P. Buchwalter A. Deutsch R. R. Horton K. A. Jenkins Y. H. Kwark G. McVicker C. S. Patel R. J. Polastre C. Schuster A. Sharma S. M. Sri-Jayantha C. W. Surovic C. K. Tsang B. C. Webb S. L. Wright S. R.(More)
dimensional silicon integration J. U. Knickerbocker P. S. Andry B. Dang R. R. Horton M. J. Interrante C. S. Patel R. J. Polastre K. Sakuma R. Sirdeshmukh E. J. Sprogis S. M. Sri-Jayantha A. M. Stephens A. W. Topol C. K. Tsang B. C. Webb S. L. Wright Three-dimensional (3D) silicon integration of active devices with through-silicon vias (TSVs), thinned(More)
technology with through-silicon vias and low-volume leadfree interconnections K. Sakuma P. S. Andry C. K. Tsang S. L. Wright B. Dang C. S. Patel B. C. Webb J. Maria E. J. Sprogis S. K. Kang R. J. Polastre R. R. Horton J. U. Knickerbocker Three-dimensional (3D) integration using through-silicon vias (TSVs) and low-volume lead-free solder interconnects allows(More)
System-on-chip (SOC) and system-on-package (SOP) technologies each have advantages depending on application needs. As system architects and designers leverage ever-increasing CMOS technology densities, a range of two and three dimensional silicon integration technologies are emerging which likely support next generation high-volume electronic applications(More)
with C4 technology B. Dang S. L. Wright P. S. Andry E. J. Sprogis C. K. Tsang M. J. Interrante B. C. Webb R. J. Polastre R. R. Horton C. S. Patel A. Sharma J. Zheng K. Sakuma J. U. Knickerbocker Three-dimensional (3D) integration technology promises to continue enhancing integrated-circuit system performance with high bandwidth, low latency, low power, and(More)
The technique used to align liquid crystals-rubbing the surface of a substrate on which a liquid crystal is subsequently deposited-has been perfected by the multibillion-dollar liquid-crystal display industry. However, it is widely recognized that a non-contact alignment technique would be highly desirable for future generations of large, high-resolution(More)
This paper presents a three-dimensional (3D) fully integrated high-speed multiphase voltage regulator. A complete switched-inductor regulator is integrated with a four-plane NoC in a two-high chip stack combining integrated magnetics, through-silicon vias (TSVs), and 45-nm SOI CMOS devices. Quasi-V 2 hysteretic control is implemented over eight(More)
  • 1