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—A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6-m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without low-threshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter(More)
—This paper presents a 1-W, class-E power amplifier that is implemented in a 0.35-m CMOS technology and suitable for operations up to 2 GHz. The concept of mode locking is used in the design, in which the amplifier acts as an oscillator whose output is forced to run at the input frequency. A compact off-chip microstrip balun is also proposed for output(More)
—We present an adaptive digital technique to calibrate pipelined analog-to-digital converters (ADCs). Rather than achieving linearity by adjustment of analog component values, the new approach infers component errors from conversion results and applies digital postprocessing to correct those results. The scheme proposed here draws close analogy to the(More)
— A monolithic 1.9-GHz, 198-mW, 0.6-m CMOS receiver which meets the specifications of the Digital Enhanced Cordless Telecommunications (DECT) standard is described. All of the RF, IF, and baseband receiver components, with the exception of the frequency synthesizers, have been integrated into a single chip solution. A description is given of a wide-band IF(More)
—An aIgoritbmic analog-to-digital conversion technique is described which is capable of achieving high-resolution conversion without the use of matched capacitors in an MOS technology. The exact integral multiplication of the signal required by the conversion is realized through an algorithmic circuit method which involves charge summing with an MOS(More)
This paper presents the opportunities and challenges for scaling A/D converters into ultra-deep-submicron CMOS technologies. With faster transistors and better matching, the trend is to migrate into higher sample rates with lower resolutions. Limited dynamic range at low supply voltages remains the utmost challenge for high-resolution Nyquist converters,(More)
A 3. 3 V c o n t i n u o u s-t i m e a n t i-a l i a s i n g fi l t e r, 8 t h-o r d e r switched-capacitor channel filter and 10-bit ADC implemented in 0.6 micron CMOS for baseband channel filtering in direct conversion cordless phone receivers realizes an overall gain of 50dB with 42dB of gain control range. Dynamic range of the combined filter section is(More)