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—A self-calibrating analog-to-digital converter employing binary weighted capacitors and resistor strings is described. Lhlearity errors are corrected by a simple digital algorithm. A folded cascode CMOS comparator resolves 30 pV in 3 ps. An experimental converter fabricated using a 6 pm gate CMOS process demonstrates 15 blt resolution and linearity at a 12(More)
—We present an adaptive digital technique to calibrate pipelined analog-to-digital converters (ADCs). Rather than achieving linearity by adjustment of analog component values, the new approach infers component errors from conversion results and applies digital postprocessing to correct those results. The scheme proposed here draws close analogy to the(More)
The increasing demand for small-form-factor, wireless devices motivates research on highly-integrated, low-cost transmitters [1]. This work describes techniques that potentially allow implementation of the transmitter at higher levels of integration than previously achieved. A prototype CMOS IC for a narrow-band PCS system operating at 1.75GHz includes two(More)
— A monolithic 1.9-GHz, 198-mW, 0.6-m CMOS receiver which meets the specifications of the Digital Enhanced Cordless Telecommunications (DECT) standard is described. All of the RF, IF, and baseband receiver components, with the exception of the frequency synthesizers, have been integrated into a single chip solution. A description is given of a wide-band IF(More)