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—A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6-m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without low-threshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter(More)
—This paper presents a 1-W, class-E power amplifier that is implemented in a 0.35-m CMOS technology and suitable for operations up to 2 GHz. The concept of mode locking is used in the design, in which the amplifier acts as an oscillator whose output is forced to run at the input frequency. A compact off-chip microstrip balun is also proposed for output(More)
—A self-calibrating analog-to-digital converter employing binary weighted capacitors and resistor strings is described. Lhlearity errors are corrected by a simple digital algorithm. A folded cascode CMOS comparator resolves 30 pV in 3 ps. An experimental converter fabricated using a 6 pm gate CMOS process demonstrates 15 blt resolution and linearity at a 12(More)
—We present an adaptive digital technique to calibrate pipelined analog-to-digital converters (ADCs). Rather than achieving linearity by adjustment of analog component values, the new approach infers component errors from conversion results and applies digital postprocessing to correct those results. The scheme proposed here draws close analogy to the(More)
  • Andrew Masami Abo, Paul R Gray, Bernhard E Boser, Ilan Adler, Chair
  • 1999
Design for Reliability of Low-voltage, Analog, switched-capacitor circuits play a critical role in mixed-signal, analog-to-digital interfaces. They implement a large class of functions, such as sampling , filtering, and digitization. Furthermore, their implementation makes them suitable for integration with complex, digital-signal-processing blocks in a(More)
The growing importance of wireless media for voice and data communications is driving a need for higher integration in personal communications transceivers to achieve lower cost, smaller form factor, and lower power dissipation [1]. One approach to this problem is to integrate the RF functionality in low-cost CMOS technology together with the baseband(More)
—A highly integrated 1.75-GHz 0.35-m CMOS transmitter is described. The modulator-based transmitter facilitates integration through the use of a unique mixer, termed a harmonic rejection mixer, and a wide loop bandwidth phase-locked loop (PLL) for the RF synthesizer. The harmonic-rejection mixers are used to eliminate the need for a discrete IF filter and(More)
  • Jacques C Rudell, Jia-Jiunn Ou, Thomas Byunghak Cho, George Chien, Francesco Brianti, Jeffrey A Weldon +1 other
  • 1997
— A monolithic 1.9-GHz, 198-mW, 0.6-m CMOS receiver which meets the specifications of the Digital Enhanced Cordless Telecommunications (DECT) standard is described. All of the RF, IF, and baseband receiver components, with the exception of the frequency synthesizers, have been integrated into a single chip solution. A description is given of a wide-band IF(More)