Paul M. Chau

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An approach toward ath-oriented tirnii-driven place-{ t ment is proposed. We rst transform the p acement with timing constraints to a Lagrange problem, A primal-dual a.ppro~ IS USed to find the optimrd relative module loca-tlons. In each primal dual iteration, the primal problem is solved by a piecewise linear resistive network method, whale the dual(More)
A new real-time IIR filter s t r u c t u r e is presented t h a t possesses exact phase linearity with 10-1000 times fewer general multiplies t h a n conventional FIR filters of similar performance a n d better magnitude characteristics t h a n equiripple o r maximally flat g r o u p delay IIR filters. This s t r u c t u r e is based on a novel technique(More)
The execution time or estimated execution time of actor. UBS Unbounded buffer synchronization. A synchronization protocol that must be used for feedforward edges of the synchronization graph. This protocol requires four synchronization accesses per iteration period. t v () v 68 Glossary Same as with the DFG understood from context. If there is no path in(More)
A new wire lengih estimation technique is presented. Wire length distribution is modeled by wire density on a 2-dimensional lattice. Assuming a point-wise independent branching process, the wire length distribution is found by solving the neighborhood density equations. For several industrial circuits tested, this technique gives an average 9. O% of(More)
New portable signal-processing applications such as mobile telephony, wireless computing, and personal digital assistants place stringent power consumption limits on their constituent components. Substantial power savings can be realized if 5 V designs are translated to use the new lower supply voltage standards. This conversion, however, is not achieved(More)
An area and computational-time efficient turbo decoder implementation on a reconfigurable processor is presented. The turbo decoder takes advantage of the latest sliding window algorithms to produce a design with minimal storage requirements as well as offering the ability to configure key system parameters via software. The parameter programmability allows(More)
In this article, we present the BinDCT algorithm, a fast approximation of the Discrete Cosine Transform, and its efficient VLSI architectures for hardware implementations. The design objective is to meet the real-time constrain in embedded systems. Two VLSI architectures are proposed. The first architecture is targeted for low complexity applications such(More)