Paul E. Landman

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The growing demand for portable electronic devices has led to an increased emphasis on power consumption within the semiconductor industry. As a result, designers are now encouraged to consider the impact of their decisions not only on speed and area, but also on power throughout the entire design process. In order to evaluate how well a particular design(More)
Low-Power Architectural Design Methodologies by Paul Eric Landman Doctor of Philosophy in Engineering Electrical Engineering and Computer Sciences University of California at Berkeley Professor Jan M. Rabaey, Chair In recent years, power consumption has become a critical design concern for many VLSI systems. Nowhere is this more true than for portable,(More)
Prompted by demands for portability and low-cost packaging, the electronics industry has begun to view power consumption as a critical design criteria. As such there is a growing need for tools that can accurately predict power consumption early in the design process. Many high-level power analysis tools don’t adequately model activity, however, leading to(More)
A CAD environment for low-power design is presented. The environment supports a high-level approach to power reduction, emphasizing optimizations at the algorithm and architecture levels of abstraction. This methodology is consistent with current state-of-the-art techniques for low-power design. The framework consists of a set of analysis and optimization(More)
This paper describes a novel strategy for generating accurate black-box models of datapath power consumption at the architecture level. This is achieved by recognizing that power consumption in digital circuits is affected by activity, as well as physical capacitance. Since existing strategies characterize modules for purely random inputs, they fail to(More)
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