Patrizia Cavalloro

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– The growing complexity of devices to be designed and manufactured, and the need to reduce the time–to–market, stress the importance of sound design methodologies. In this framework formal synthesis has the advantage of increasing the quality both of the design process and of the realized devices. The problem of relating the different abstraction levels(More)
High potentialities in terms of abstraction and re-use for hw design are offered by the recently proposed innovative extensions to VHDL, implementing object-oriented techniques. In this paper we evaluate the results of modelling ATM cells in Objective VHDL, exploiting the language features in terms of abstraction and reuse. The selected modules are(More)
The lack of a general methodology and notation has been identified as one of the main obstacles bedeviling system-on-chip designers. Nevertheless, there is a lot of confusion about what SLD (System Level Design) means and which SLDL (System Level Design Language) is the most appropriate. With SOC demands there has been recently high interest in system level(More)