Patrizia Cavalloro

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High potentialities in terms of abstraction and re-use for hw design are offered by the recently proposed innovative extensions to VHDL, implementing object-oriented techniques. In this paper we evaluate the results of modelling ATM cells in Objective VHDL, exploiting the language features in terms of abstraction and reuse. The selected modules are(More)
The growing complexity of devices to be designed and manufactured, and the need to reduce the time–to–market, stress the importance of sound design methodologies. In this framework formal synthesis has the advantage of increasing the quality both of the design process and of the realized devices. The problem of relating the different abstraction levels(More)
The industrial interest in the application of formal methods in the design of complex ASICs is noteworthy to improve the efficiency of the design process (reduced time-to-market) and t o increase the quality of the final products (increased competitive profile). In this paper we focus our attention on design capture and functional verification, two critical(More)
Italsim is a simulation system developed to model and simulate a printed circuit board (PCB) manufacturing plant. The primary contribution of the system is its display of the efficacy of the knowledge-based approach as applied to a real-world simulation problem. The system utilises the Integrated Modeling Package (IMP), a software package developed(More)
The test problem increasingly affects system design process, related costs and time to market. Requirements from VLSI/WSI manufacturers are for fast and reliable testability tools, with the possibility of their introduction in early phases of design. In this paper we describe the different abstraction levels at which testability analysis will be applied in(More)