Patrick Scheer

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Today, measurement of 65 nm CMOS technology demonstrates Ft around 200 GHz and Fmax higher than 250 GHz as stated in G. Dambrine et al. (2005), which are clearly comparable to advanced commercially available 100 nm III-V HEMT or state-of-the-art SiGe HBT based in P. Chevalier et al. (2004). This increase allows new millimeter wave (MMW) applications on(More)
This paper presents the status of most advanced CMOS and BiCMOS technologies able to address very high-speed optical communications and millimeter-wave applications. The performance of active and passive devices available on bulk Si and high-resistivity SOI is reviewed and HF characteristics of state-of-the-art SiGe HBTs and MOSFETs are compared. The(More)
In this paper, we present a process/design co-optimization methodology for a full-SOC platform based on 28nm LP CMOS technology with high-k metal-gate (HK/MG) architecture. We report a CPU critical path speed enhancement by implementing a triple gate oxide scheme (so called 28LPG) on HK/MG scheme combined with 20fF/um2 MiM solution for decoupling(More)
This paper presents a 14nm technology designed for high speed and energy efficient applications using strain-engineered FDSOI transistors. Compared to the 28nm FDSOI technology, this 14nm FDSOI technology provides 0.55× area scaling and delivers a 30% speed boost at the same power, or a 55% power reduction at the same speed, due to an increase in(More)
65 nm n-MOSFETs show state-of-the-art cut-off frequency with f<sub>t</sub> = 210 GHz and microwave low noise and high gain properties (NF<sub>min</sub> = 0.8 dB and G<sub>ass</sub> = 17.3 dB at 12 GHz). As compared with the previous nodes, the high frequency properties of these MOSFETs continue to be in agreement with the downscaling trends.
In the framework of MOSFET reliability for RF/AMS applications, a deep investigation of RF parameters degradation is performed. An innovative flow, composed of DC and RF stresses with DC and RF aging characterization, is presented. Degradation kinetics of main parameters are physically explained and modeled using PSP compact model to predict the behavior of(More)
A detailed presentation of the latest version of the Leti-UTSOI compact model is provided. Leti-UTSOI2 is the first available model able to describe the behavior of low-doped ultrathin body and buried oxide fully depleted silicon-on-insulator transistors in all bias configurations, including strong forward back bias. In this part, a full analytical(More)
An investigation of parasitic coupling that occurs when making on-wafer measurement at millimeter wave range is described. Several passive structures-dedicated to de-embedding of MOSFETs-are experimentally studied and compared to HFSS electromagnetic simulations in order to highlight parasitic coupling and identify causes of measurement errors. Suggestions(More)
Continuous CMOS improvement has been achieved in recent years through strain engineering for mobility enhancement. Nevertheless, as transistor pitch is scaled down, conventional strain elements (as embedded stressors, stress liners) are loosing their effectiveness [1]. The use of strained materials for the channel to boost performance is thus essential. In(More)