Patrick M. Mills

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Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be exploited when fed by high instruction bandwidth. This task is the responsibility of the instruction fetch unit. Accurate branch prediction and low I-cache miss ratios are essential(More)
Optimization of instruction fetch mechanisms for high issue rates.ory disambiguation using the memory conflict buffer. Speculative disambiguation: A compilation technique for dynamic memory disambiguation. Contrasting characteristics and cache performance of technical and multiuser commercial workloads. cache: a low latency approach to high bandwidth(More)
Recent superscalar processors issue four instructions per cycle. These processors are also powered b y highly-parallel superscalar cores. The potential performance c an only be exploited when fed by high instruction bandwidth. This task is the responsibility of the instruction fetch unit. Accurate branch prediction and low I-cache miss ratios are essential(More)
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