Patrick M. Mills

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Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be exploited when fed by high instruction bandwidth. This task is the responsibility of the instruction fetch unit. Accurate branch prediction and low I-cache miss ratios are essential(More)
Until recently, the serialization constraints induced by true data dependences have been regarded as an absolute limit--the data-flow limit--on the parallel execution of serial programs. Likewise, the exact detection and enforcement of these dependences has been assumed to be a requirement for semantically correct execution. This paper introduces the weak(More)
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