Patrick Loumeau

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| In this paper, the design procedure for a third-order continuous-time modulator with RZ feedback is described. The circuit is realized using continuous-time current-mode integrators and DACs with switched-current sources. A design method to nd the minimum biasing current required to achieve the desired dynamic range is presented. With a sampling frequency(More)
High-pass ∆Σ modulator has the advantage of immunity from the low frequency noise and is thus very effective in the parallel architectures. In this paper, we present the behavioral modelling and simulation of ∆Σ modulators in VHDL-AMS, and in particular of the high-pass modulator. A set of models in VHDL-AMS suitable for time-domain be-havioral simulation(More)
This paper deals with the problem of clock skew errors in time-interleaved analog-to-digital converters. Deterministic sample-time errors between time-interleaved channels generate nonlinear distortion and degrade SFDR. We propose a fully digital calibration method that uses, on the one hand, adaptive FIR filters to reconstruct a correctly sampled signal(More)
| In this paper, a design method for continuous-time mod-ulators with RZ feedback pulse is proposed. This method is used to design a second-order continuous-time modulator. The circuit is realized using continuous-time current-mode in-tegrators and switched-current sources DAC. The eeect of the integrator thermal noise and non-ideal RZ feedback pulse on the(More)
Contribution à l'élaboration de méthodologies et d'outils d'aide à la conception de systèmes multi-technologiques Soutenance le 27 novembre 2003 devant le jury composé de A mes parents, à mes soeurs, à mon frère, et à mon épouse Houda 3 Ecole Nationale Supérieure des Télécommunications REMERCIEMENTS Le travail présenté dans cette thèse a été effectué au(More)