Patrick Loumeau

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A Sample and Hold circuit using the 0.6 pm technology for low frequency application is presented. This circuit is based on a specific memory base cell that reduces the error caused by the output conductance. It works with a 3.3 V supply voltage, offers high-resolution and low power dissipation. Simulations results presented a -77.6 dB harmonic distortion(More)
This article presents the optimization process for a new architecture of digital-enhanced radio frequency receiver. This receiver is based on combining charge sampling filters and hybrid filter banks techniques. We describe the structure optimization based on a compromise between performance and implementation constraints. We then show the performances(More)
High-pass /spl Delta//spl Sigma/ modulator has the advantage of immunity from the low frequency noise and is thus very effective in the parallel architectures. In this paper, we present the behavioral modelling and simulation of /spl Delta//spl Sigma/ modulators in VHDL-AMS, and in particular of the high-pass modulator. A set of models in VHDL-AMS suitable(More)
In previous work, a non-uniform sampling (NUS) technique to control analog-to-digital conversion (ADC) in a multistandard radio receiver was proposed. In this context of wide band radio signals, the NUS-based ADC offers the advantages of relaxing antialiasing filter (AAF) constraints, decreasing the sampling frequency average and reducing ADC dynamic power(More)
Nowadays, communication devices are supporting an increasing number of standards. The diversity of the requirements in terms of speed and resolution, makes the design of a single low power analog to digital converter (ADC) suitable for all the scenarios very problematic. Reconfigurable ADCs are a solution to this problem, where resolution would be exchanged(More)
This paper deals with dynamic latch hysterisys and its effects on ∆Σ modulators. It sheds light on the difference between its impact on low pass and high pass modulators. It also presents a technique to reduce its effect on low pass ∆Σ modulators. This technique was tested using a 2 order feed forward ∆Σ modulator. The employed dynamic latch was designed in(More)