Patrick J. Eibl

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We present an error detection technique for a floating point adder which uses a checker adder of reduced precision to determine if the result is correct within some error bound. Our analysis establishes a relationship between the width of the checker adder’s mantissa and the worst-case magnitude of an undetected error in the primary adder’s result. This(More)
Recently, several researchers have proposed schemes for low-cost, low-power error detection in the processor core. In this work, we demonstrate that one particular scheme, an enhanced implementation of the Argus framework called Argus-2, is a viable option for industry adoption. Using an FPGA prototype, we experimentally evaluate Argus-2's ability to detect(More)
The purpose of this work is to experimentally demonstrate that a synthesis and implementation of existing ideas can achieve the goal of a low-cost, soft-error-tolerant multicore processor. We show that a multicore processor can be designed that tolerates the vast majority of soft errors, with area, power, and performance costs that are within 20% of a(More)
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