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As processor core counts increase, networks-on-chip (NoCs) are becoming an increasingly popular interconnec-tion fabric due to their ability to supply high bandwidth. However, NoCs need to deliver this high bandwidth at low latencies, while keeping within a tight power envelope. In this paper, we present a novel NoC with hybrid interconnect that leverages… (More)
without affecting the performance of the receive amplifier. These circuit techniques enable a high level of I/O integration to relieve the pin bandwidth bottleneck of modern VLSI chips.
We describe a low-cost wearable system that tracks the location of individuals indoors using commonly available inertial navigation sensors fused with radio frequency identification (RFID) tags placed around the smart environment. While conventional pedestrian dead reckoning (PDR) calculated with an inertial measurement unit (IMU) is susceptible to sensor… (More)
A 4Gb/s serial link tracking clock and data recovery (CDR) circuit fabricated in 0.24µm CMOS technology dissipates 84mW and occupies 0.3mm 2. The input signal is 2× oversampled by 8 offset-cancelled receive amplifiers per receive clock cycle. The samples are processed by a phase controller to position the receive clocks at the center and the edge of the… (More)
(250‐word limit) The rapid scaling of microprocessors has shifted the critical bottleneck of high‐performance computing systems from the computational units to the communication infrastructure. By taking advantage of the parallelism and capacity of dense wavelength‐division‐multiplexed (DWDM) technology, optical interconnects using nanophotonics offer a… (More)
Biomedical signals exhibit substantial variance in their sparsity, preventing conventional a-priori open-loop setting of the compressed sensing (CS) compression factor. In this work, we propose, analyze, and experimentally verify a rate-adaptive compressed-sensing system where the compression factor is modified automatically, based upon the sparsity of the… (More)
A wirelessly-powered, near-threshold, body area network SoC supporting synchronized multi-node TDMA operation is demonstrated in 65nm CMOS. A global clock source sent from a base-station wirelessly broadcasts at 434.16MHz to all sensor nodes, where each individual BAN sensor is phase-locked to the base-station clock using a super-harmonic injection-locked… (More)
The total area of each receiver is 0.0174 mm 2 , resulting in a measured power efficiency of 0.6 mW/Gb/s.