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As processor core counts increase, networks-on-chip (NoCs) are becoming an increasingly popular interconnec-tion fabric due to their ability to supply high bandwidth. However, NoCs need to deliver this high bandwidth at low latencies, while keeping within a tight power envelope. In this paper, we present a novel NoC with hybrid interconnect that leverages(More)
  • M.-J Edward Lee, William J Dally, John W Poulton, Patrick Chiang, Stephen F Greenwood
  • 2001
A 4Gb/s serial link tracking clock and data recovery (CDR) circuit fabricated in 0.24µm CMOS technology dissipates 84mW and occupies 0.3mm 2. The input signal is 2× oversampled by 8 offset-cancelled receive amplifiers per receive clock cycle. The samples are processed by a phase controller to position the receive clocks at the center and the edge of the(More)
(250‐word limit) The rapid scaling of microprocessors has shifted the critical bottleneck of high‐performance computing systems from the computational units to the communication infrastructure. By taking advantage of the parallelism and capacity of dense wavelength‐division‐multiplexed (DWDM) technology, optical interconnects using nanophotonics offer a(More)
ŠNEXT-GENERATION COMPUTING systems, from high-performance server farms to battery-constrained mobile devices, consist of several microchips on a single PCB substrate. Although current CMOS scaling allows the future integration of several heterogeneous chips on a single die, future computing platforms will also contain many specialized chips from several(More)
—While Moore's law scaling continues to double transistor density every technology generation, supply voltage reduction has essentially stopped, increasing both power density and total energy consumed in conventional microprocessors. Therefore, future processors will require an architecture that can: a) take advantage of the massive amount of transistors(More)