Patricia Sagmeister

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The design of most systems-on-a-chip (SoC) architectures rely on simulation as a means for performance estimation. Such designs usually start with a parameterizable template architecture, and the design space exploration is restricted to identifying the suitable parameters for all the architectural components. However, in the case of heterogeneous SoC(More)
The paper describes the need for early analysis tools to enable developers of today's system-on-a-chip (SoC) designs to take advantage of pre-designed components, such as those found in the IBM Blue Logic ® Library, and rapidly explore high-level design alternatives to meet their system requirements. We report on a new approach for developing high-level(More)
High-profile web servers often become the victim of web server overload Distributed Denial-of-Service (DDoS) attacks. Motivations of such attacks range from technical challenge (e.g. script kiddies) to financial profit (e.g. blackmailing the web server's owner). This paper presents the DIADEM Firewall architecture that allows an ISP to protect its customers(More)
We present a design methodology for a modular network processor architecture that leads to a balanced, service-defined mix between programmable processor cores, configurable hardware assists, and specialized coprocessors. Whereas the processor cores address the flexibility and extendibility needs of the networking market, the hardware components offload the(More)
This thesis discusses techniques for sharing the processing load among multiple processing units within systems that act as nodes in a data communications network. Load-sharing techniques have been explored in the field of computer science for many years and their benefits are well known, including better utilization of processing capacity and enhanced(More)
Network processors use highly parallel architectures to improve performance and reach multi-gigabit line-speeds. In this paper, we emulate a pipeline in a highly parallel non-programmable industrial InfiniBand Host Channel Adapter to make a performance and bottleneck analysis and, at the same time, explore the potential of a pipelined architecture.(More)
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