Pascal Witte

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This paper presents a third order, single-loop, continuous-time modulator with an internal 4-bit quantizer. The modulator is sampled at 500 MHz, and features an oversampling ratio of only 10. Therefore, DAC linearization by dynamic element matching is ineffective, and the DAC nonlinearities are not corrected within the modulator loop but in the subsequent(More)
There is ongoing effort to realize low-power ΔΣ ADCs with more than 10MHz bandwidth (BW) – especially for wireless transceivers. Besides the trend to make these ADCs more reconfigurable [1], recent advances in the design of CT ΔΣ modulators focused on design improvements [2], on replacing analog by digital circuits [3, 4], or on avoiding costly multi-bit(More)
In this paper we review a background digital DAC linearization technique for Delta-Sigma analog-to-digital converters (∆Σ ADCs). A description of the theory behind this technique, details on a modulator implementation, measurement results, and finally an outlook for enhancing this technique for bandpass ∆Σ ADCs is provided. The technique has been(More)
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