Parastoo Nikaeen

Learn More
The track-and-hold stage at the front-end of high-speed, high-resolution ADCs is usually the limiting factor in their linearity performance at high input frequencies. In this paper, we propose a digital correction algorithm for the dynamic errors generated in this stage. The digital post-processing scheme uses circuit insight and judicious modeling of the(More)
Practical simulation and measurement methods based on impulse sensitivity functions to characterize the sampling aperture of clocked comparators are demonstrated on a 90nm CMOS testchip. The results comparing a StrongARM latch and a CML latch suggest that the StrongARM latch has a narrower aperture of 23ps but its aperture center is more sensitive to supply(More)
A digital technique for the compensation of dynamic nonlinearities at the front-end of high-speed, high-resolution ADCs is presented. The complexity of the digital post-processing scheme is minimized using judicious modeling of the relevant nonidealities. Applying the method to a 14-bit, 155-MS/s ADC provides &gt; 83 dB SFDR up to f<sub>in</sub> = 470 MHz.(More)
A synthesized compact model of substrate coupling resistance for lightly doped substrate processes is proposed. The model incorporates all geometrical parameters including geometrical mean distance with a few process-dependent fitting coefficients. The model accuracy is shown to be within 15% error using the measurement data from two test chips, one in a(More)
  • 1