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We introduce a SAT based automatic abstraction refinement framework for model checking systems with several thousand state variables in the cone of influence of the specification. The abstract modelâ€¦ (More)

Satisfiability procedures have shown significant promise for symbolic simulation of large circuits, hence they have been used in many formal verification techniques, including automated abstractionâ€¦ (More)

We describe a methodology for verifying system-on-chip designs. In our methodology, the problem of verifying system-on-chip designs is decomposed into three tasks. First, we verify, once and for all,â€¦ (More)

Some ratio estimators for estimating the population mean of the variable under study, which make use of information regarding the population proportion possessing certain attribute, are proposed.â€¦ (More)

In this paper exponential ratio and exponential product type estimators using two auxiliary variables are proposed for estimating unknown population variance y S . Problem is extended to the case ofâ€¦ (More)

- Pankaj Chauhan, Edmund M. Clarke, Daniel Kroening
- Proceedings. 41st Design Automation Conferenceâ€¦
- 2004

Parametric representations used for symbolic simulation of circuits usually use BDDs. After a few steps of symbolic simulation, state set representation is converted from one parametricâ€¦ (More)

- Pankaj Chauhan, Edmund M. Clarke, Somesh Jha, James H. Kukula, Helmut Veith, Dong Wang
- CHARME
- 2001

Model checking is the process of verifying whether a model of a concurrent system satisfies a specified temporal property. Symbolic algorithms based on Binary Decision Diagrams (BDDs) haveâ€¦ (More)

- Pankaj Chauhan, Edmund M. Clarke, +4 authors Dong Wang
- IEEE/ACM International Conference on Computerâ€¦
- 2001

Computing the set of states reachable in one step from a given set of states, i.e. <i>image computation,</i> is a crucial step in several symbolic verification algorithms, including <i>modelâ€¦ (More)

- Pankaj Chauhan, Deepak Goyal, Gagan Hasteer, Anmol Mathur, Nikhil Sharma
- 2009 46th ACM/IEEE Design Automation Conference
- 2009

We present a novel technique for Sequential Equivalence Checking (SEC) between non-cycle-accurate designs. The problem is routinely encountered in verifying the correctness of a system-level modelâ€¦ (More)

- Randal E. Bryant, Pankaj Chauhan, Edmund M. Clarke, Amit Goel
- FMCAD
- 2000

We propose a model for modular synchronous systems with combinational dependencies and define consistency using this model. We then show how to derive this model from a modular specification whereâ€¦ (More)