Panagiotis Chaourani

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Accurate and fast estimation of the static power consumption in various design corners for nanoscale integrated circuits is a very important task since it facilitates power and noise analysis procedures. The power contributor approach which is based on the separability of the power components can be used for this purpose. In this paper, parametric models(More)
A new analytical model for the CMOS inverter is introduced. This model results by solving analytically the differential equation which describes the inverter operation. It uses new simplified transistor current expressions which are developed taking into account the nanoscale effects and also considering temperature as a parameter. Expressions for the(More)
The Monolithic 3D (M3D) integration technology has emerged as a promising alternative to dimensional scaling thanks to the unprecedented integration density capabilities and the low interconnect parasitics that it offers. In order to support technological investigations and enable future M3D circuits, M3D design methodologies, flows and tools are essential.(More)
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