Panagiota Vatsolaki

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Switch chips are building blocks for computer and communication systems. Switches need internal buffering, because of output contention; shared buffering is known to perform better than multiple input queues or buffers, and the VLSI implementation of the former is <i>not</i> more expensive than the latter. We present a new organization for a shared buffer(More)
We describe the queue management block of ATLAS I , a single-chip ATM switch (router) with optional credit-based (backpressure) flow control. ATLAS I is a 4-million-transistor 0.35-micron CMOS chip, currently under development, offering 20 Gbit/s aggregate I/O throughput, sub-microsecond cut-through latency, 256-cell shared buffer containing multiple(More)
Although ATM (Asynchronous Transfer Mode), is a widely accepted standard for WANs (Wide Area Networks), it has not yet been widely embraced by the NOW community, because (i) most current ATM switches (and interfaces) have high latency, and and (ii) they drop cells when (even short-term) congestion happens. In this paper, we present ATLAS I, a single-chip(More)
Modern networks of workstations connected by Gigabit net works have the ability to run high performance computing applications at a reasonable performance but at a signi cantly lower cost The per formance of these applications is usually dominated by their e ciency of the underlying communication mechanisms However e cient communi cation requires that not(More)
Although ATM Asynchronous Transfer Mode is a widely accepted standard for WANs Wide Area Networks it has not yet been widely embraced by the NOW community because i most current ATM switches and interfaces have high latency and and ii they drop cells when even short term congestion happens In this paper we present ATLAS I a single chip ATM switch with Gbits(More)
We present the sampling and decoding algorithm and the VLSI implementation of a high-speed UART (Universal Asynchronous ReceiverTransmitter) library cell to be used in custom or semi-custom VLSI chip designs. Our approach to data recovery, which is based on signal preprocessing and an innovative decoding algorithm, operates with as few as 2 samples per bit(More)
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