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The goal of functional validation of a high-level synthesis system is to assert, with a reasonable degree of confidence, that the layouts generated by the high-level synthesis system correctly implement the specified behavior. This paper presents a systematic approach to functional validation based on the analysis of specification language constructs,(More)
The multicompact synthesis (MSS) integrated design environment for multichip modules (MCMs) is discussed. The MSS environment is centered in VHDL (very-high-speed integrated circuit hardware description language), WAVES (waveform and vector exchange specification), and PDL (performance description language). MSS provides four levels of automated synthesis(More)
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