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We introduce a new non-intrusive on-chip cache-tuning hardware module capable of accurately predicting the best configuration of a configurable cache for an executing application. Previous dynamic cache tuning approaches change the cache configuration several times as part of the tuning search process, executing the application using inferior configurations(More)
Due to the large contribution of the memory subsystem to total system power, the memory subsystem is highly amenable to customization for reduced power/energy and/or improved performance. Cache parameters such as total size, line size, and associativity can be specialized to the needs of an application for system optimization. In order to determine the best(More)
Numerous variations of configurable caches, having variable parameters like total size, line size, and associativity, have been proposed in commercial microprocessors in recent years. Tuning a configurable cache to a target application has been shown to reduce memory-access power by over 50%. However, searching the configuration space for the best(More)
This paper presents the cache configuration exploration of a programmable system, in order to find the best matching between the architecture and a given application. Here, programmable systems composed by processor and memories may be rapidly simulated making use of ArchC, an Architecture Description Language (ADL) based on Sys-temC. Initially designed to(More)
This paper presents an environment based on SystemC for architecture specification of programmable systems. Making use of the new architecture description language ArchC, able to capture the processor description as well as the memory subsystem configuration, this environment offers support for system-level specification, intended for platform-based design.(More)
Configurable caches can significantly reduce energy consumption by adapting the system's cache configuration to the applications' specific requirements to meet system design and optimization goals. However, large configuration design spaces require prohibitive design space exploration time (e.g., due to lengthy design space analyses, simulations, and/or(More)
Today's digital systems design requires extensive system-level simulation to ensure that the right architectural trade-offs are made. In platform based designs a large number of platforms models must be executed for tuning the platform for the application. In order to run these simulations with adequate performance, design architects have increasingly(More)
Configurable cache tuning architectures for embedded systems applications can dramatically reduce energy consumption. Existing state-of-the-art heuristics to efficiently explore large configurable cache design space has aimed at finding the cache configuration that yields the minimal energy consumption. However, as energy-driven cache optimizations may(More)
This paper describes a VLSI architecture for classification of multi-and hyperspectral imagery using Fuzzy Logic with trapezoidal membership functions. The fuzzy classifier is implemented using a rule-based approach, where each class is defined as a set of sub rules. There is only one sub rule associated to each band within a class. Each sub rule is(More)
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