Pablo I. Balzola

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In this paper, we present a full-static carry-skip adder designed to achieve low power dissipation and high-performance operation. To reduce the adder's delay and power consumption, the adder is divided into variable-sized blocks that balance the inputs to the carry chain. The optimum block sizes for minimizing the critical path delay with complementary(More)
ÐHigh-speed multiplication is frequently used in general-purpose and application-specific computer systems. These systems often support integer multiplication, where two n-bit integers are multiplied to produce a 2n-bit product. To prevent growth in word length, processors typically return the n least significant bits of the product and a flag that(More)
Parallel saturating multioperand adders significantly improve the performance of GSM speech coders by giving compilers and assembly language programmers the ability to parallelize loops containing saturating dot products, while maintaining GSM compliant results. This paper presents four designs for parallel saturating multioperand adders. These designs have(More)
We present the design of a carry skip adder that achieves low power dissipation and high-performance operation. The carry skip adder's delay and power dissipation are reduced by dividing the adder into variable-sized blocks that balance the delay of inputs to the carry chain. This grouping reduces active power by minimizing extraneous glitches and(More)
We present a tier 2 Software Defined-Radio platform (SDR), built around the latest Sandbridge Technologies’ multithreaded Digital Signal Processor (DSP) SB3500, along with the description of major design steps taken to ensure the best radio link and computational performance. This SDR platform is capable of executing 4G wireless communication standards such(More)
To meet the exponential increase in processing requirements of present day embedded system applications, System-On-Chip (SoC) designs increasingly have multiple processing elements on the same die. The functionality of these processing elements varies considerably, and includes hardware accelerators for specific Digital Signal Processing (DSP) kernels,(More)
We discuss the hardware and software challenges in building a 2 Mbit per second wireless handheld communications device. Of primary importance is power dissipation. A host of new techniques are required at all levels of the design hierarchy. Innovative VLSI circuit techniques combined with low power process technologies will provide opportunities for high(More)
This paper presents designs for parallel saturating multioperand adders. These adders have only a single carrypropagate adder on the critical delay path, yet produce the same results that would be obtained if the additions were performed serially with saturation after each operation. When used with parallel saturating multipliers or multiplyaccumulate(More)
High-speed multiplication is frequently used in general-purpose and application-specific computer systems. These systems often support integer multiplication, where two n-bit integers are multiplied to produce a 2n-bit product. To prevent growth in word length, processors typically return the n least significant bits of the product and a flag that indicates(More)