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POLUS: A POwerful Live Updating System
This paper presents POLUS, a software maintenance tool capable of iteratively evolving running software into newer versions. POLUS's primary goal is to increase the dependability of contemporaryExpand
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The Superthreaded Processor Architecture
The common single-threaded execution model limits processors to exploiting only the relatively small amount of instruction-level parallelism that is available in application programs. TheExpand
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Live updating operating systems using virtualization
Many critical IT infrastructures require non-disruptive operations. However, the operating systems thereon are far from perfect that patches and upgrades are frequently applied, in order to closeExpand
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Processor Self-Scheduling for Multiple-Nested Parallel Loops
Processor self-scheduling is a useful scheme in a multiprocessor system if the execution time of each iteration in a parallel loop is not known in advance and varies substantially, or if there areExpand
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The superthreaded architecture: thread pipelining with run-time data dependence checking and control speculation
This peeper presents a new concurrent multiple-threaded architectural model, called superthreading, for exploiting thread-level parallelism on a processor. This architectural model adopts a threadExpand
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HQEMU: a multi-threaded and retargetable dynamic binary translator on multicores
Dynamic binary translation (DBT) is a core technology to many important applications such as system virtualization, dynamic binary instrumentation and security. However, there are several factorsExpand
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Distributing Hot-Spot Addressing in Large-Scale Multiprocessors
When a large number of processors try to access a common variable, referred to as hot-spot accesses in [6], not only can the resulting memory contention seriously degrade performance, but it can alsoExpand
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Managing shared last-level cache in a heterogeneous multicore processor
Heterogeneous multicore processors that integrate CPU cores and data-parallel accelerators such as GPU cores onto the same die raise several new issues for sharing various on-chip resources. TheExpand
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Design and Implementation of a Lightweight Dynamic Optimization System
Many opportunities exist to improve micro-architectural performance due to performance events that are dicult to optimize at static compile time. Cache misses and branch mis-prediction patterns mayExpand
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Dynamic Software Updating Using a Relaxed Consistency Model
Software is inevitably subject to changes. There are patches and upgrades that close vulnerabilities, fix bugs, and evolve software with new features. Unfortunately, most traditional dynamic softwareExpand
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