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- P. Restle, T.G. McNamara, +13 authors B.D. McCredie
- 2000 Symposium on VLSI Circuits. Digest ofâ€¦
- 2000

A global clock distribution strategy implemented on several microprocessor chips is described. The clock network consists of buffered, tunable tree networks, with the final trees all driving a commonâ€¦ (More)

The clock distribution on the Power4 dual-processor chip supplies a single critical 1.5 GHz clock from one SOI-optimized PLL to 15,200 pins on a large chip with 20 ps skew and 35 ps jitter. Theâ€¦ (More)

- S K Chan, K. L. Shepard, P. Restle
- IEEE Journal of Solid-State Circuits
- 2005

This work presents a new approach to global clock distribution in which tree-driven grids are augmented with on-chip spiral inductors to resonate the clock capacitance. In this scheme, the energy ofâ€¦ (More)

- C.J. Anderson, John G. Petrovick, +22 authors Bojan J Zoric
- 2001 IEEE International Solid-State Circuitsâ€¦
- 2001

The fourth-generation POWER processor chip contains 170M transistors and includes 2 microprocessor cores, shared L2, directory for an off-chip L3, and all logic needed to interconnect multiple chipsâ€¦ (More)

- S K Chan, P. Restle, K. L. Shepard, N A James, R. Franch
- 2004 IEEE International Solid-State Circuitsâ€¦
- 2004

A resonant global clock-distribution network operating at 4.6GHz is designed in a 90nm 1.0V CMOS technology. Unique to this approach is the set of on-chip spiral inductors that resonate with theâ€¦ (More)

- S K Chan, K. L. Shepard, P. Restle
- IEEE Journal of Solid-State Circuits
- 2006

This paper presents a distributed differential oscillator global clock network where the clock capacitance is rendered resonant with a set of on-chip spiral inductors. The clock amplitude and clockâ€¦ (More)

- Yuan Taur, D. S. Zicherman, +6 authors G. G. Shahidi
- IEEE Electron Device Letters
- 1992

A shift-and-ratio method for extracting MOSFET channel length is presented. In this method, channel mobility can be any function of gate voltage, and high source-drain resistance does not affectâ€¦ (More)

- S K Chan, K. L. Shepard, P. Restle
- ISSCC. 2005 IEEE International Digest ofâ€¦
- 2005

A distributed differential oscillator global clock network using on-chip spiral inductors is designed in a 0.18 /spl mu/m 1.8V CMOS technology. The 2mm/spl times/2mm resonant clock network has a tankâ€¦ (More)

- M.G.R. Thomson, P. Restle, N A James
- 2006 IEEE International Solid State Circuitsâ€¦
- 2006

Microprocessor global clock distribution networks use long buffered wires where reflections can be significant. Using accurate transmission-line models and optimization, these reflection effects canâ€¦ (More)

- G. A. Sai-Halasz, M. R. Wordeman, +9 authors R. H. Dennard
- IEEE Electron Device Letters
- 1987

The first device performance results are presented from experiments designed to assess FET technology feasibility in the 0.1-Âµm gate-length regime. Low-temperature device design considerations forâ€¦ (More)