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Making Scheduling "Cool": Temperature-Aware Workload Placement in Data Centers
TLDR
This paper examines a theoretic thermodynamic formulation that uses information about steady state hot spots and cold spots in the data center and develops real-world scheduling algorithms, and develops an alternate approach to address the problem of heat management through temperature-aware workload placement.
Heracles: Improving resource efficiency at scale
TLDR
Heracles is presented, a feedback-based controller that enables the safe colocation of best-effort tasks alongside a latency-critical service and dynamically manages multiple hardware and software isolation mechanisms to ensure that the latency-sensitive job meets latency targets while maximizing the resources given to best- Effort tasks.
Single-ISA heterogeneous multi-core architectures for multithreaded workload performance
TLDR
This paper examines two single-ISA heterogeneous multi-core architectures in detail, demonstrating dynamic core assignment policies that provide significant performance gains over naive assignment, and even outperform the best static assignment.
Consistent and Durable Data Structures for Non-Volatile Byte-Addressable Memory
TLDR
This paper presents Consistent and Durable Data Structures (CDDSs), a single-level data store that, on current hardware, allows programmers to safely exploit the low-latency and non-volatile aspects of new memory technologies.
No "power" struggles: coordinated multi-level power management for the data center
TLDR
This paper proposes and validate a power management solution that coordinates different individual approaches and performs a detailed quantitative sensitivity analysis to draw conclusions about the impact of different architectures, implementations, workloads, and system design choices.
Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction
TLDR
This paper proposes and evaluates single-ISA heterogeneous multi-core architectures as a mechanism to reduce processor power dissipation and results indicate a 39% average energy reduction while only sacrificing 3% in performance.
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
TLDR
This paper proposes and evaluates single-ISA heterogeneousmulti-core architectures as a mechanism to reduceprocessor power dissipation and results indicate a 39% average energy reduction while only sacrificing 3% in performance.
GViM: GPU-accelerated virtual machines
TLDR
GViM is presented, a system designed for virtualizing and managing the resources of a general purpose system accelerated by graphics processors and how such accelerators can be virtualized without additional hardware support.
JouleSort: a balanced energy-efficiency benchmark
TLDR
This work proposes and motivate JouleSort, an external sort benchmark, for evaluating the energy efficiency of a wide range of computer systems from clusters to handhelds, and demonstrates a Joule sort system that is over 3.5x as energy-efficient as last year's estimated winner.
FREE-p: Protecting non-volatile memory against both hard and soft errors
TLDR
Free-p protects against both hard and soft errors and can be extended to chipkill, and increases NVRAM lifetime by up to 26% over the state-of-the-art even with severe process variation while performance degradation is less than 2% for the initial 7 years.
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