• Publications
  • Influence
SystemC - a modeling platform supporting multiple design abstractions
  • P. R. Panda
  • Computer Science
  • International Symposium on System Synthesis (IEEE…
  • 30 September 2001
TLDR
SystemC is a C++ based modeling platform supporting design abstractions at the register transfer, behavioral, and system levels. Expand
  • 202
  • 17
  • PDF
On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems
TLDR
We present a technique for efficiently exploiting on-chip Scratch-Pad memory by partitioning the application's scalar and arrayed variables into off-chip DRAM and on-Chip SRAM, with the goal of minimizing the total execution time of embedded applications. Expand
  • 240
  • 9
  • PDF
Efficient utilization of scratch-pad memory in embedded processor applications
TLDR
We present a technique for efficiently exploiting on-chip Scratch-Pad memory by partitioning the application's scalar and array variables into off-chip DRAM and on-Chip SRAM, with the goal of minimizing the total execution time of embedded applications. Expand
  • 291
  • 8
  • PDF
Data and memory optimization techniques for embedded systems
TLDR
We present a survey of the state-of-the-art techniques used in performing data and memory-related optimizations in embedded systems. Expand
  • 369
  • 7
  • PDF
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
From the Publisher: Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration covers techniques for optimization of system-level memory requirements, and exploration of candidateExpand
  • 176
  • 7
Augmenting Loop Tiling with Data Alignment for Improved Cache Performance
TLDR
We present a technique that augments loop tiling with data alignment, achieving improved efficiency (by ensuring that the cache is never under-utilized) as well as improved flexibility (by eliminating self-interference cache conflicts independent of the tile size). Expand
  • 106
  • 5
Low-power memory mapping through reducing address bus activity
  • P. R. Panda, N. Dutt
  • Computer Science
  • IEEE Trans. Very Large Scale Integr. Syst.
  • 1 September 1999
TLDR
We exploit regularity and spatial locality in the memory accesses and determine the mapping of behavioral array references to physical memory locations to minimize address bus transitions. Expand
  • 86
  • 4
Data Memory Organization and Optimizations in Application-Specific Systems
TLDR
In application-specific designs, customized memory organization expands the search space for cost-optimized solutions. Expand
  • 65
  • 4
  • PDF
Power-efficient System Design
This book addresses power optimization in modern electronic and computer systems. Several forces aligned in the past decade to drive contemporary computing in the direction of low power andExpand
  • 68
  • 4
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