• Publications
  • Influence
A 10–Bit 1.6-GS/s 27-mW Current-Steering D/A Converter With 550-MHz 54-dB SFDR Bandwidth in 130-nm CMOS
  • P. Palmers, M. Steyaert
  • Engineering, Computer Science
  • IEEE Transactions on Circuits and Systems I…
  • 1 November 2010
TLDR
This paper presents a 10-bit 5-5 segmented current- steering digital-to-analog converter implemented in a standard 130-nm CMOS technology. Expand
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A 130 nm CMOS 6-bit Full Nyquist 3 GS/s DAC
TLDR
This paper presents a 6-bit very high-speed, low-power digital-to-analog converter (DAC). Expand
  • 60
  • 8
A 130 nm CMOS 6-bit full nyquist 3GS/s DAC
TLDR
This paper presents a 6-bit high-speed, low-power digital-to-analog converter (DAC). Expand
  • 74
  • 6
Variation-Aware Structural Synthesis of Analog Circuits via Hierarchical Building Blocks and Structural Homotopy
TLDR
This paper presents MOJITO-R, a tool that performs variation-aware structural synthesis of analog circuits. Expand
  • 40
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Trustworthy Genetic Programming-Based Synthesis of Analog Circuit Topologies Using Hierarchical Domain-Specific Building Blocks
TLDR
This paper presents MOJITO, a system that performs structural synthesis of analog circuits, returning designs that are trustworthy by construction. Expand
  • 45
  • 2
Parallel-path digital-to-analog converters for Nyquist signal generation
TLDR
Nyquist-rate digital-to-analog converters (DACs) can generate frequencies up to half the sampling frequency. Expand
  • 32
  • 2
Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit Topologies
TLDR
This paper presents MOJITO, a system which optimizes across thousands of analog circuit topologies simultaneously, and returns a set of sized topologies that collectively provide a performance tradeoff. Expand
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  • PDF
Automated extraction of expert knowledge in analog topology selection and sizing
TLDR
This paper presents a methodology for analog designers to maintain their insights into the relationship among performance specifications, topology choice, and sizing variables, despite those insights being constantly challenged by changing process nodes and new specs. Expand
  • 11
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Massively multi-topology sizing of analog integrated circuits
TLDR
This paper demonstrates a system that performs multi-objective sizing across 100,000 analog circuit topologies simultaneously, with SPICE accuracy. Expand
  • 27
A linear 28nm CMOS digital transmitter with 2×12bit up to LO baseband sampling and −58dBc C-IM3
TLDR
This paper presents a 1.2-2.6GHz 2×12 bit Direct Digital RF Modulator (DDRM) realized in 28nm CMOS. Expand
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