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Flash memory cells-an overview
TLDR
Basic operations and charge-injection mechanisms that are most commonly used in actual flash memory cells are reviewed to provide an understanding of the underlying physics and principles in order to appreciate the large number of device structures, processing technologies, and circuit designs presented in the literature.
Estimate of signal probability in combinational logic networks
Two methods for the calculation of node signal probabilities in combinational networks are presented. These techniques provide a better accuracy than existing algorithms and a deeper insight in the
High-field-induced degradation in ultra-thin SiO/sub 2/ films
Very thin thermal oxides are shown to exhibit a failure mode that is undetected by conventional breakdown tests. This failure mode appears in the form of excessive leakage current at low field and is
Fundamental variability limits of filament-based RRAM
While Resistive RAM (RRAM) are seen as an alternative to NAND Flash, their variability and cycling understanding remain a major roadblock. Extensive characterizations of multi-kbits RRAM arrays
Novel design for testability schemes for CMOS ICs
The authors present ideas for addressing the problem of detecting non-stuck-at faults in CMOS circuits that cannot be revealed by means of conventional methods (i.e., as logical errors in the
Testability measures in pseudorandom testing
The authors present two methods for computing the fault detection probabilities in combinational networks. The methods provide a deeper insight into the effects of signal correlations caused by
Quantum-mechanical modeling of accumulation layers in MOS structure
An original method is used for the quantum-mechanical modeling of n-type silicon accumulation layers. Unlike previous methods, which were only valid near 4.2 K, the approach is valid up to room
An analytical model for the aliasing probability in signature analysis testing
The Markov chain model of linear feedback shift-registers (LFSRs) for signature analysis testing is analytically solved to obtain the exact expression of the aliasing error probability as a function
Experimental Investigation of 4-kb RRAM Arrays Programming Conditions Suitable for TCAM
TLDR
Extensive characterizations of multi-kb RRAM arrays during forming, set, reset, and cycling operations are presented, and the relationships among programming conditions, memory window, and endurance features are presented.
Oxide-thickness determination in thin-insulator MOS structures
A technique to electrically determine the oxide thickness (and, in some cases, the flat-band voltage and surface doping as well) of thin-insulator MOS structures is discussed. This method does not
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