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Spin transfer torque (STT)-MRAM--based runtime reconfiguration FPGA circuit
TLDR
Spin transfer torque (STT)-based MRAM is then evaluated to address these issues, some design techniques and novel computing architecture for FPGA logic circuits based on STT-MRAM are presented in this article. Expand
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Failure and reliability analysis of STT-MRAM
TLDR
This paper classifies firstly all the possible failures of STT-MRAM into “soft errors” and “hard errors“, and analyzes their impact on the memory reliability. Expand
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New non-volatile Logic based on Spin-MTJ
TLDR
In this paper, hybrid STT-based MTJ (spin-MTJ)/CMOS logic circuits and some design techniques are proposed based on STMicroelectronics 90 nm CMOS technology and the published Hitachi spin- MTJ technology. Expand
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Design considerations and strategies for high-reliable STT-MRAM
TLDR
In this paper, we address these issues from circuit design point of view and present some efficient solutions. Expand
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16 nm planar NMOSFET manufacturable within state-of-the-art CMOS process thanks to specific design and optimisation
In nanometer MOSFETs, because of the small channel size, mesoscopic and even quantum effects can come into play. We have fabricated l6 nm NMOS devices featuring I/sub on/=400 /spl mu/A//spl mu/m andExpand
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Comparative Assessment of GST and GeTe Materials for Application to Embedded Phase-Change Memory Devices
TLDR
This work presents a thorough comparative assessment of undoped GST and GeTe active phase-change (PC) materials for application to embedded memory devices (in particular consumer and automotive products). Expand
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A capacitor-less DRAM cell on 75nm gate length, 16nm thin fully depleted SOI device for high density embedded memories
A capacitor-less DRAM cell on very thin film (Tsi=16nm) and short gate length (Lg=75nm) fully depleted (FD) device is demonstrated for the first time. Memory operations mechanisms are presented andExpand
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Highly performant double gate MOSFET realized with SON process
Utilizing the SON (silicon on nothing) process, highly performant double gate devices have been processed in a planar configuration. Two families of devices were obtained (high performance and lowExpand
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50 nm-Gate All Around (GAA)-Silicon On Nothing (SON)-devices: a simple way to co-integration of GAA transistors within bulk MOSFET process
For the first time, both GAA and bulk devices were shown to be operational on the same chip. Not all issues have been solved yet (gate materials, access resistance) but already the first-try resultsExpand
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Cross-Point Architecture for Spin-Transfer Torque Magnetic Random Access Memory
TLDR
Spin-transfer torque magnetic random access memory (STT-MRAM) is considered as one of the most promising candidates to build a true universal memory thanks to its fast write/read speed, infinite endurance, and nonvolatility. Expand
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