• Publications
  • Influence
Toward Increasing FPGA Lifetime
TLDR
In this work, we analyze the impact of two different types of hard errors, namely, Time- Dependent Dielectric Breakdown (TDDB) and Electromigration (EM) on FPGAs, from both the performance and reliability perspective. Expand
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A low-power phase change memory based hybrid cache architecture
TLDR
We investigate the architectural challenges in integrating a PRAM based memory into the conventional cache hierarchy for deep-sub micron CMOS designs. Expand
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FLAW: FPGA lifetime awareness
TLDR
We demonstrate the vulnerability of field programmable gate arrays to two different types of hard errors, namely, time dependent dielectric breakdown (TDDB) and electro-migration. Expand
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Thermal-aware reliability analysis for platform FPGAs
TLDR
We present a dynamic thermal-aware reliability management (DTRM) framework to analyze the impact of temperature variations on the longterm/lifetime reliability of Platform FPGAs. Expand
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Thermal-aware reliability analysis for Platform FPGAs
TLDR
We present a dynamic thermal-aware reliability management (DTRM) framework to analyze the impact of temperature variations on the longterm/lifetime reliability of Platform FPGAs. Expand
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Lifetime Reliability Aware Design Flow Techniques for Dual-Vdd Based Platform FPGAs
TLDR
The proposed reliability aware design flow techniques achieve anaverage of 65.8% and 75% improvement in lifetime of LUTs and interconnect wires respectively. Expand
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Efficient Function Evaluations with Lookup Tables for Structured Matrix Operations
TLDR
A hardware efficient approach is introduced for elementary function evaluations in certain structured matrix computations that exploits the function properties and the matrix structures to claim better control over numerical dynamic ranges. Expand
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TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platform
TLDR
We describe TANOR an automated tool for designing hardware accelerators for the class of N-body interaction problems that supports both algorithmic and architectural exploration. Expand
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An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization
  • J. Kim, L. Deng, +7 authors X. Sun
  • Computer Science
  • IEEE Transactions on Computers
  • 1 December 2009
TLDR
This paper describes TANOR, an automated framework for designing hardware accelerators for numerical computation on reconfigurable platforms. Expand
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Exploiting clock skew scheduling for FPGA
TLDR
In this paper, we present an analysis of several design structural constraints that affect the CSS and propose techniques to resolve these constraints. Expand
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