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Design Of A Modified Ultra Low Power , High Precision CMOS Opamp based Comparator for Biomedical Applications
In this paper we have represented an improved design of Two stage Opamp based Cmos Comparator having ultra low power consumption which is beneficial in many low power applications such as manyExpand
SYNTHESIS OF 128 BIT ADVANCED ENCRYPTION STANDARD ALGORITHM USING VHDL
TLDR
AES encryption is based on an iterative round-looping architecture .Which provide lowest area. Expand
SYNTHESIS OF DOUBLE PRECISION FLOAT- ING POINT MULTIPLIER USING VHDL
TLDR
Synthesis of double precision floating point multiplier using VHDL using pipelining technique . Expand
Synthesis And Simulation Of 8x8-Bit Modified Booth's Multiplier
The booth’s algorithm is the most frequently used method for multiplication. This algorithm allows the reduction in the number of partial products to be compressed in the carry adder. Thus theExpand
FPGA Implementation of CORDIC Algorithm Architecture
CORDIC algorithm is very simple and iterative process for performing various mathematical computations. Most of the literature lacks in calculation of resources utilized by a particular CORDICExpand
An Efficient Field Programmable Gate Array Implementation of Double Precision Floating Point Multiplier using VHDL
TLDR
This paper presents an efficient FPGA implementation of double precision floating point multiplier using VHDL. Expand
Synthesis of 64 Standard Algorithm using VHDL
Data security is the most important requirement of today’s world, to transmit digital data from one place to another. We need to secure the transmitted data at the transmitting end so that noExpand
FPGA Implementation of Double Precision Floating Point Multiplier using Xilinx Coregen Tool
Floating point arithmetic is widely used in many areas, especially scientific computation and signal processing. The main applications of floating points today are in the field of medical imaging,Expand
Field Programmable Gate Array Implementation of 14 bit Sigma-Delta Analog to Digital Converter
TLDR
This paper the design and FPGA implementation of a delta sigma A/D convertor. Expand
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