• Publications
  • Influence
A 2-V 10.7-MHz CMOS limiting amplifier/RSSI
TLDR
This paper presents low-voltage low-power CMOS circuit design techniques for an intermediate frequency (IF) limiting amplifier and received signal strength indicator (RSSI). Expand
  • 104
  • 8
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A 3.3-V CMOS wideband exponential control variable-gain-amplifier
TLDR
A CMOS cascadable variable gain amplifier (VGA) with exponential gain control characteristic is presented. Expand
  • 85
  • 4
A 0.003 mm$^{2}$ 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching
TLDR
This paper describes a single-channel, calibration-free Successive-Approximation-Register (SAR) ADC with a resolution of 10 bits at 240 MS/s. Expand
  • 48
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A Low-Power CMOS Linear-in-Decibel Variable Gain Amplifier With Programmable Bandwidth and Stable Group Delay
TLDR
This brief presents a new circuit architecture for linear-in-decibel, constant-bandwidth variable gain amplifier (VGA). Expand
  • 52
  • 3
Random Swapping Dynamic Element Matching Technique for Glitch Energy Minimization in Current-Steering DAC
TLDR
Dynamic element matching (DEM) has been employed to increase the spurious-free dynamic range of data converters. Expand
  • 40
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A Battery-Less, Implantable Neuro-Electronic Interface for Studying the Mechanisms of Deep Brain Stimulation in Rat Models
TLDR
This paper proposes a battery-less, implantable neuro-electronic interface suitable for studying DBS mechanisms with a freely-moving rat. Expand
  • 57
  • 2
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The HOY Tester-Can IC Testing Go Wireless?
TLDR
We propose HOY - a novel wireless test system with enhanced embedded test features. Expand
  • 25
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A 1.2-V CMOS Limiter / RSSI / Demodulator for Low-IF FSK Receiver
TLDR
This paper presents low-voltage low-power limiter, RSSI, and demodulator designs for a low-IF wireless FSK receiver. Expand
  • 26
  • 2
A 1 V Input, 3 V-to-6 V Output, 58%-Efficient Integrated Charge Pump With a Hybrid Topology for Area Reduction and an Improved Efficiency by Using Parasitics
TLDR
This paper presents an integrated hybrid 6-stage voltage multiplier without using high-voltage-tolerant devices. Expand
  • 19
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Joint Polynomial and Look-Up-Table Predistortion Power Amplifier Linearization
TLDR
We propose a joint polynomial and LUT predistorter for PA linearization. Expand
  • 57
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