• Publications
  • Influence
All-MOS charge redistribution analog-to-digital conversion techniques. I
Describes a technique for performing A/D conversion compatibly with standard single-channel MOS technology. The use of a binary weighted capacitor array to perform a high-speed, successiveExpand
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A 1.75 GHz highly-integrated narrow-band CMOS transmitter with harmonic-rejection mixers
A 1.75 GHz transmitter with harmonic and double image reject mixer integrates the full signal path from the DAC to the RF output with two frequency synthesizers in a 0.35 /spl mu/m double-polyExpand
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  • Open Access
All-MOS charge-redistribution analog-to-digital conversion techniques. II
For pt.I see ibid., vol.SC-10, no.6, p.371-9 (1975). Describes techniques for performing A/D conversion compatibly with standard single-channel MOS technology. This second paper describes aExpand
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A self-calibrating 15 bit CMOS A/D converter
A self-calibrating analog-to-digital converter using binary weighted capacitors and resistor strings is described. Linearity errors are corrected by a simple digital algorithm. A folded cascode CMOSExpand
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  • Open Access
A ratio-independent algorithmic analog-to-digital conversion technique
An algorithmic analog-to-digital conversion technique is described which is capable of achieving high-resolution conversion without the use of matched capacitors in an MOS technology. The exactExpand
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An effective gate resistance model for CMOS RF and noise modeling
A physics-based effective gate resistance model representing the non-quasi-static (NQS) effect and the distributed gate electrode resistance is proposed for accurately predicting the RF performanceExpand
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  • Open Access
A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications
  • G. Chien, P. Gray
  • Computer Science
  • IEEE Journal of Solid-State Circuits
  • 1 December 2000
A monolithic CMOS local oscillator utilizing a delay-locked loop (DLL)-based frequency multiplier technique to synthesize a 900-MHz carrier frequency with a low close-in phase noise is described. TheExpand
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A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR
A 1.8-V 14-b 12-MS/s pseudo-differential pipeline analog-to-digital converter (ADC) using a passive capacitor error-averaging technique and a nested CMOS gain-boosting technique is described. TheExpand
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  • Open Access
MOS operational amplifier design-a tutorial overview
  • P. Gray, R. Meyer
  • Computer Science
  • IEEE Journal of Solid-State Circuits
  • 1 December 1982
Presents an overview of current design techniques for operational amplifiers implemented in CMOS and NMOS technology at a tutorial level. Primary emphasis is placed on CMOS amplifiers because ofExpand
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  • Open Access
A 1.9 GHz wide-band IF double conversion CMOS integrated receiver for cordless telephone applications
A number of recent efforts have concentrated on highly-integrated radio receivers using a low-cost silicon process such as CMOS. This prototype monolithic CMOS receiver combines RF and basebandExpand
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