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Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop
TLDR
In this paper, a new technique for implementing low-energy double-edge triggered flip-flops is introduced. Expand
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Low-Power Clocked-Pseudo-NMOS Flip-Flop for Level Conversion in Dual Supply Systems
  • P. Zhao, J. McNeely, +5 authors L. Downey
  • Engineering, Computer Science
  • IEEE Transactions on Very Large Scale Integration…
  • 1 September 2009
Clustered voltage scaling (CVS) is an effective way to decrease power dissipation. One of the design challenges is the design of an efficient level converter with fewer power and delay overheads. InExpand
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Noise-tolerant high fan-in dynamic CMOS circuit design
TLDR
We propose a new circuit technique that makes domino dynamic CMOS more robust and more noise-tolerant with minimal performance degradation and energy overhead. Expand
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A double-edge implicit-pulsed level convert flip-flop
TLDR
In this paper, we propose a novel implicit-pulsed level convert flip-flop that uses circuit techniques such as conditional discharge to reduce the overhead incurred with level conversion flip-Flops (LCFF). Expand
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A new gate-level body biasing technique for PMOS transistors in subthreshold CMOS circuits
TLDR
We propose a new body biasing technique for PMOS transistors working in the subthreshold region that improves circuit performance over DTPMOS and consumes less power. Expand
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A Low Power Domino with Differential-Controlled-Keeper
TLDR
A new domino circuit structure is shown that reduces the power-delay-product over 16% as compared to previous domino techniques with keepers. Expand
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Contention reduced/conditional discharge flip-flops for level conversion in CVS systems
TLDR
In this paper, we propose novel level conversion flip-flops with less delay, and power consumption overhead. Expand
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Low Power Design of Double-Edge Triggered Flip-Flop by Reducing the Number of Clocked Transistors
In this paper, a new technique for implementing low energy double-edge triggered flip-flops is introduced. The new technique employs a clock branch shared (CBS) scheme to reduce the number of clockedExpand
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On gate leakage reduction in dynamic CMOS circuits
TLDR
In this paper we propose a new leakage reduction circuit technique for domino dynamic CMOS circuits with no performance degradation and with minimal area overhead. Expand
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