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A 1-V, 8-bit pipelined ADC is realized using multi-phase switched-opamp (SO) technique. A novel loading-free architecture is proposed to reduce the capacitive loading and to improve the speed in low-voltage SO circuits. Employing the proposed loading-free pipelined ADC architecture together with double-sampling technique and a fast-wake-up(More)
A 1-V WLAN IEEE 802.11a CMOS transceiver integrates all building blocks on a single chip including a transformer-feedback VCO and a stacked divider for the frequency synthesizer and 8-bit IQ ADCs and 8-bit IQ DACs. Fabricated in a 0.18-mum CMOS process and operated at a single 1-V supply, the receiver and the transmitter consume 85.7 mW and 53.2 mW,(More)
A monolithic output-ripple-based buck converter with adaptive output and ultra-fast reference tracking is presented. Fixed-switching-frequency V<sup>2</sup>-control is used in steady-state operation; while its speed limitation during reference tracking is eliminated by employing end-point prediction, a novel oscillator with clock-holding function, and the(More)
A 1V WLAN IEEE 802.11a CMOS transceiver integrates all building blocks on a single chip including a transformer-feedback VCO and a stacked divider for the synthesizer and 8-bit IQ ADCs and 8-bit IQ DACs. Fabricated in a 0.18-mum CMOS process and operated at a single 1-V supply, the receiver and the transmitter consume 85.7mW and 53.2mW, including the(More)
Given the high costs of conducting a drug-response trial, researchers are now aiming to use retrospective analyses to conduct genome-wide association studies (GWAS) to identify underlying genetic contributions to drug-response variation. To prevent confounding results from a GWAS to investigate drug response, it is necessary to account for concomitant(More)
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