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1 Hysteresis eects All the I SD-V G plots of our devices were accompanied by hysteresis. Fig. S1 (a) shows the channel current of Sample C as a function of gate voltage V G for V SD = 5 V. An increase in V G to 40 V is accompanied by monotonic increase in I SD from ∼1 nA to ∼100 µA. However, with decreasing V G from 40 V to zero (sequence 6-7-8), the(More)
We study the resistive switching (RS) mechanism as a way to obtain multilevel cell (MLC) memory devices. In an MLC, more than 1 b of information can be stored in each cell. Here, we identify one of the main conceptual difficulties that prevented the implementation of RS-based MLCs. We present a method to overcome these difficulties and to implement a 6-b(More)
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