P. R. Balasubramanian

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Current workflow management systems do not provide adequate support for workflow modeling. Real life work processes are much richer in variations and more dynamic than is expressed in a typical workflow model. Users need to be able to adjust workloads and modify workflow models on-the-fly. In addition, data about workflow executions are analyzed with(More)
GDI (gate diffusion input) based technique for low power combinational logic circuit design has been elaborately discussed and the advantage of this design style over static CMOS (SC) implementation and pass-transistor logic (PTL), with regard to power consumption, delay and area complexity is also described in recent literature (Morgenshtein, 2002). In(More)
The recent increase in the volatility of E-business environments and the increasing need for enterprise to participate in business webs, have forced enterprises to contemplate outsourcing key business services to Application Service Providers (ASPs)-entities that deploy, host, and manage access to applications delivered over networks on a subscription(More)
We present a parallel implementation of three transmission switching algorithms. The first is based on a parallel search of all candidate lines, the second is based on a priority listing of lines and the third is based on decomposing the set of candidate lines in smaller subsets that are solved in parallel. We present a duality result that justifies the(More)
We explore how a collection of models and related modeling knowledge could be made available over an organizational Intranet. The objective is to create an environment that will enable sharing and re-use of models and will promote collaborative work on models. Because of their widespread use in organizations, we will focus on spreadsheet models to(More)
– A novel circuit topology for the CMOS based Incrementer/Decrementer circuit is presented in this paper. The design methodology is extensively based on Domino logic and it utilizes a simple two level look-ahead structure. The highly parallel, regular structure of the proposed 8-bit decision module (DM) macro cell makes this design, especially advantageous(More)
In this work, the authors consider the problem of logic minimization for a special class of Boolean networks, targeting low power implementation, using static CMOS logic. The authors start by framing a new binary minterm-value (BmV) matrix/binary max term-value (BMV) matrix for a binary 2-tuple, [mi (Mi), mj (Mj)], where HD (mi (Mi), mj (Mj)) is O(n), where(More)