P. P. Zode

Learn More
– This paper presents a novel approach to design a four and eight parallel pipelined fast Fourier transform (FFT) architecture based on canonic signed digit multiplier. This approach is based on use of decimation in time algorithm which reduces the number of delay elements up to some extent compared to decimation in frequency based design. The number of(More)
After analyzing the advantages and disadvantages of all the general algorithms adopted in designing square root on FPGA chips with pipeline technology, a proposed algorithm based on digit by digit calculation method is discussed. The algorithm is realized on the ModelSim SE 6.3f development platform with VHDL language and the simulation results show that it(More)
  • 1