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This paper introduces the concept of rate privacy in the context of wireless sensor networks. Our discussion reveals that the concept indeed is of a great importance for the privacy preservation of such networks. As a result, we propose a buffering scheme to protect the rate from adversaries. Simulation results verify the applicability of our approach.
A 26-32GHz quadrature cascaded phase locked loop (PLL) is presented. The PLL is implemented in 65nm bulk CMOS, consuming 27mW and has less than 100fsec integrated jitter with -114.4 and -112.6dBc/Hz phase noise at 1MHz offset for integer and fractional modes, respectively.
With the growth in computing needs, energy cost includes a large portion of operating cost of cloud data centers. Electricity prices vary in different times and geographical places. Such diversity provides opportunity for diminishing total cost via migration of jobs to places with lower energy prices. Most of the previous studies only focus on computing… (More)
Finding the location of an object has become very popular in recent years. Several control and monitoring solutions for commercial and industrial applications are introduced in the literature. Many of them use wireless networks or GSM cellular data to find the physical location of an object or a wireless node with respect to a reference point. This paper… (More)
This paper introduces a quadrature fractional-N cascaded frequency synthesizer and its phase noise analysis, optimization, and design for future 5G wireless transceivers. The performance improvement of the cascaded phase-locked loop (PLL) over single-stage PLL in terms of jitter and power consumption is theoretically presented and verified with measured… (More)