A gigahertz analog multiplier based on OTA and squaring is proposed. The multiplier has gigahertz frequency response is suitable to use in communication system. The circuit is based on 0.18 µm CMOS technology simulated using PSPICE level 7. This technique provides; wide dynamic range, GHz-bandwidth response and low power consumption. The proposed circuit… (More)
This paper proposes a high frequency four-quadrant CMOS current multiplier circuit using low voltage supply. This circuit has frequency response about 15 GHz, using V 1 ± supply voltage and has input range about A µ 15 ±. All CMOSs operate in saturation region and the simulation results are based on 0.18 m µ CMOS technology achieved using HSPICE (Level 49).
This paper studies the adaptive FEC control algorithms to improve control the amount of redundancy. The recently adaptive FEC " CNR algorithm " considers the history of packet loss in the network before changing the amount of redundancy and does not waste time. The performance of the CNR algorithm is used for simulation model. The smoothing parameter is… (More)