P. Igic

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Realising a higher voltage application utilising bridge topologies in CMOS Power IC CMOS technology presents integration and design issues that must be solved by careful selection of the manufacturing process architecture. In this paper, we present a solution that uses a p+/p-buffer/n-epi stack to implement a 100 V RESURF N-channel LDMOS high-side(More)
A standard 0.35 micrometer CMOS technology has been extended for 100 V Power IC applications by accommodating reduced surface field (RESURF) LDMOSFET device with p-well block region or extended poly-overlap region for suppression of the drain wrapping potential. A 100 V integrated H-bridge circuit suitable for driving a brushless DC motor has been designed,(More)
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