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We present a novel CMOS current-mode imager that uses nonvolatile floating gate charge storage in the pixel for automatic cancellation of fixed-pattern noise (FPN) caused by fabrication process variations. We demonstrate the ability to reduce the variance of the initial FPN over a range of incident light intensities. Each pixel incorporates a unique circuit(More)
A hybrid dark-active address-event representation (AER) imager has been designed, simulated and laid out in a commercially available 0.5 /spl mu/m CMOS process. The imager comprises a 16 /spl times/ 16 array of tunable active pixels each of which is approximately 33 /spl times/ 30 /spl mu/m/sup 2/ in area, with a 19% fill factor. It operates both in: (1) an(More)
Amplifier performance can be severely degraded by the presence of intrinsic physical noise sources. We analyze the information transfer rates for simple and wide-range operational transconductance amplifiers (OTAs) using the principles of information theory. Frequency transfer characteristics and input-referred noise of both simple and wide-range OTAs are(More)
The paper shows how to take advantage of device temperature operating characteristics to obtain a temperature sensor, and use it to help generate a low-power temperature-insensitive oscillator. The oscillator serves as a carrier frequency generation circuit in an on-off-keying (OOK) transceiver system. We have described a low power temperature insensitive(More)
We describe an adaptive log domain second order filter with integrated learning rules. The system is implemented using multiple input floating gate transistors to realize online learning of quality factor and time constant. We use adaptive dynamical system theory to derive robust control laws for both quality factor and time constant adaptation in a system(More)
We apply the technique of floating-gate differential injection to a 1.2-GHz CMOS comparator to achieve arbitrary, accurate, and adaptable offsets. The comparator uses nonvolatile charge storage on floating-gate nodes for either offset nulling or automatic programming of a desired offset. We utilize impact-ionized pFET hot-electron injection to achieve fully(More)
The explosive growth of wireless communication market today has brought an increasing demand for high performance radio-frequency integrated circuits (RFIC) at low cost. As a result, there is a great interest in integrating the various blocks of a communication system on a single chip transceiver. One of the most difficult components to integrate is the(More)
A 6-b 750-MS/s flash analog-to-digital converter (ADC) uses nonvolatile analog storage for reference levels and achieves a signal-to-noise-plus-distortion ratio (SNDR) and a spurious-free dynamic range of 37.2 and 48.6 dB, respectively. The architecture comprises an array of adaptive floating-gate comparators that enables storage and programming of(More)
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