Owen Farnsworth

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0740-7475/02/$17.00 © 2002 IEEE September–October 2002 SCAN-BASED LOGIC TESTING using automatic test-pattern generation (ATPG) has been highly successful for testing large, complex ASICs. The shipped quality of these ASICs is a testament to our industry’s acceptance of practical DFT methodologies. As chip gate counts continue to increase, the industry will(More)
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