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Reconfigurable computing is becoming increasingly attractive for many applications. This survey covers two aspects of reconfigurable computing: architectures and design methods. Our chapter includes recent advances in reconfigurable architectures, such as the Altera Stratix II and Xilinx Virtex 4 FPGA devices. We identify major trends in general-purpose and(More)
An automated static approach for optimizing bit widths of fixed-point feedforward designs with guaranteed accuracy, called MiniBit, is presented. Methods to minimize both the integer and fraction parts of fixed-point signals with the aim of minimizing the circuit area are described. For range analysis, the technique in this paper identifies the number of(More)
We explore the design space of Field Programmable Gate Arrays (FPGAs), Processors and ASICs – Hardware-Software Tri-design – in the framework of encryption for hand-held communication units. IDEA (International Data Encryption Algorithm) is used to show the tradeoffs for the suggested technologies. The measures for comparing different options are:(More)
—Using a general polynomial approximation approach, we present an arithmetic library generator for the logarithmic number system (LNS). The generator produces optimized LNS arithmetic libraries that improve significantly over previous LNS designs on area and latency. We also provide area cost estimation and bit-accurate simulation tools that facilitate(More)
This paper presents a new division algorithm, which requires two multiplication operations and a single lookup in a small table. The division algorithm takes two steps. The table lookup and the first multiplication are processed concurrently in the first step, and the second multiplication is executed in the next step. This divider uses a single multiplier(More)
In this paper we present Minibit+, an approach that optimizes the bit-widths of fixed-point and floating-point designs, while guaranteeing accuracy. Our approach adopts different levels of analysis giving the designer the opportunity to terminate it at any stage to obtain a result. Range analysis is achieved using a combined affine and interval arithmetic(More)
We present a methodology for generating optimized architectures for data bandwidth constrained extensible processors. We describe a scalable Integer Linear Programming (ILP) formulation, that extracts the most profitable set of instruction-set extensions given the available data bandwidth and transfer latency. Unlike previous approaches, we differentiate(More)
Simplifying the programming models is paramount to the success of reconfigurable computing. We apply the principles of object-oriented programming to the design of stream architectures for reconfigurable computing. The resulting tool, StReAm, is a domain specific compiler on top of the object-oriented module generation environment PAM-Blox. Combining module(More)
We apply our object-oriented design environment PAM-Blox to dynamic generation of circuits for re-congurable computing. Our approach combines the structural hardware design environment with commercial synthesis of nite state machines (FSMs). The PAM-Blox environment features a well dened hardware object interface and the ability to control the placement of(More)