Oscar Belotti

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Abstract—This paper presents the design of a third-order Σ∆ modulator targeted for WCDMA applications. The architecture uses two operational amplifiers and distributed fully digital feed-forward paths to minimize the output swing of op-amps. Simulation results show that first and second integrator output swings are reduced by 88% and 75%, respectively.(More)
This paper presents a third-order Sigma-Delta modulator that uses only two operational amplifiers. A fully digital solution reduces both amplifiers output swings. This design achieves complex conjugate zeros that allows obtaining a signal-to-noise ratio of about 8 dB better than having all the zeros placed at z = 1. Behavioral level simulations demonstrate(More)
Methods for avoiding the slew-rate limit and the optimal design of hybrid Continuous-Time (CT) Σ∆ modulators with switched-capacitor (SC) DAC are discussed. Limitations on performance due to finite bandwidth and slew-rate of the operational amplifier are analyzed. The use of multi-rate scheme made by a set of time-interleaved SC-DAC moderates the non-linear(More)
A technique for the exact design of the noise transfer function of Continuous-Time (CT) Sigma-Delta modulators with arbitrary and multiple DAC responses and real op-amps is here presented. The approach, that presupposes linear behavior of active blocks, produces a CT modulator with the same noise shaping as its DiscreteTime counterpart. The method operates(More)
A new design approach operating in the time domain for the design of Continuous-Time (CT) Σ∆ modulators is presented. The method obtains CT modulators that are exactly equivalent to Sampled-Time (SD) counterpart without any constraint on the shape of feedback DACs responses. The procedure is suitable and powerful for transistor-level studies because design(More)
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